This application claims priority to Japanese Patent Application No. 2001-151983 filed on May 22, 2001.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and, more particularly, the present invention relates to a semiconductor circuit device which has a logic circuit including storage elements and a fault-detecting method of a semiconductor integrated circuit device.
2. Description of the Background
A conventional method for scanning a logical circuit has been widely used to detect faults, such as a stuck-at fault, in a logic circuit. This conventional method can efficiently detect faults because the value of a flip-flop (hereinafter, xe2x80x9cFFxe2x80x9d) can be directly handled using this method.
The process for detecting a fault (hereinafter, xe2x80x9ctestingxe2x80x9d) of a scanned logic circuit will now be explained with reference to the accompanying drawings.
FIG. 17 is a circuit diagram showing a scan FF as used in the prior art. This example is a scan FF with a multiplexer (hereinafter, xe2x80x9cMUXxe2x80x9d), or a MUX-type scan flip-flop (FF).
In this configuration, MUX g1702 is connected with input terminal D of a master latch g1701 constituting a FF. A signal (hereinafter, xe2x80x9cinput signal from logic circuitxe2x80x9d) which comes from logic gates (hereinafter, xe2x80x9cuser logic circuitxe2x80x9d) for normal operation at the preceding stage is input through an input signal line into g1702. Also, a signal for scan from the FF at the preceding stage (hereinafter, xe2x80x9cscan-in signalxe2x80x9d) is input through a scan-in signal line. Further, a control signal for selecting whether g1701 picks up the input signal from logic circuit or the scan-in signal (hereinafter, xe2x80x9cscan-enable signalxe2x80x9d) is input through a scan-enable signal line. Input terminal D of a slave latch g1703 is connected with output terminal Q of g1701. The output terminal of g1703 is connected with an output signal line which conveys a signal (hereinafter, xe2x80x9coutput signalxe2x80x9d) to the user logic circuit or a scan FF in a successive stage.
FIG. 18 shows a logic circuit which is scanned using the prior art. This is an example of a scanned logic circuit in which multiple MUX-type scan FFs are connected. In this configuration, scan-out signal lines of MUX-type scan FFs g1801, g1802 are connected with the scan-in signal lines of g1802 and g1803, respectively; this constitutes a signal path (hereinafter, xe2x80x9cpathxe2x80x9d). This path is referred to as a xe2x80x9cscan path.xe2x80x9d
The scan-in signal line of g1801 is connected with the terminal (hereinafter, xe2x80x9cscan-in terminalxe2x80x9d) for inputting a scan-in signal from the outside of the semiconductor integrated circuit chip while the scan-out signal line of g1803 is connected with the terminal (hereinafter, xe2x80x9cscan-out terminalxe2x80x9d) for outputting a scan-out signal to the outside of the semiconductor integrated circuit chip (hereinafter, xe2x80x9cchipxe2x80x9d).
A test procedure which utilizes scan FFs preferably takes place in the following sequence: (1) an operation for substituting an initial value for the test into each FF in the logic circuit (xe2x80x9cscan-in operationxe2x80x9d); (2) an operation for inputting the initial value from each FF into the user logic circuit and letting each FF pick up the result data for the test as an output from the user logic circuit (xe2x80x9ctesting operationxe2x80x9d); and (3) an operation for collecting the result data from each FF (xe2x80x9cscan-out operationxe2x80x9d). This sequence may be repeated. In FIG. 18, a1804, a1805, and a1806 represent signal flows for scan-in operation, testing operation, and scan-out operation, respectively.
FIG. 19 is a timing diagram showing the operation of a scan FF (g1704) as used in the prior art. First, for the scan-in operation, a scan-enable signal is set at High in order to enable each FF to pick up a scan-in signal. Also, in order to substitute the initial value for a test value in each FF, a transition of the system clock signal is made more than one time (s1901) to perform shift operations through the scan path.
Next, for the testing operation, in order to enable each FF to pick up an output signal, the scan-enable signal is set at Low (s1902). Also, a transition of the system clock signal is made a first time to input the initial value for the test into the user logic circuit and a second time for the result data for the test to be picked up by each FF (s1903).
For the scan-out operation, the scan-enable signal is set at High again in order to enable each FF to output a scan-out signal (s1904). Also, for collection of the result data for the test from each FF, a shift operation is done as in the scan-in operation.
FIG. 20 is a circuit diagram showing an exemplary internal circuit of a scan FF (g1704) as used in the prior art.
However, in a scan-in operation and a scan-out operation (collectively referred to as xe2x80x9cscan operationxe2x80x9d) the amount of state changes of the logic circuit tends to be higher than in normal user operation. Therefore, as pointed out in IEEE Computer vol.32, no.11 (p.61, 1999), with the growing tendency toward device miniaturization, fault-detecting errors due to excessive voltage drops or chip damage due to heat generation may occur.
As potential solutions to address this problem, some methods have been suggested; the Proceedings of the 11th International VLSI Test Symposium (pp.4-9, 1993) include one such method in which the logic circuit is divided into blocks which are then tested sequentially.
The way in which the logic circuit is divided into blocks and each block is tested will now be described with reference to the relevant accompanying drawings. FIG. 21 shows a logic circuit which is divided according to the prior art. In this example, the logic circuit is divided into N blocks using N+1 scan paths which consist of MUX-type scan FFs (wherein N is a natural number).
In this configuration, a selector g2102 which controls the operation of Logic 1 at the following stage is connected with the output signal line of a scan FF g2101. An output signal for normal operation and testing operation which comes from g2101 is input into g2102. In addition, a fixed signal for pausing Logic 1 is input through a boundary scan (FF) g2103. Further, a signal (pausing signal) for selecting whether to output the output signal from g2101 or the fixed signal through g2103 to Logic 1 is input through Pausing Signal Line 1. The same type of selector is connected with the output signal lines of the other scan FFs to control the operation of Logic 1 through Logic N.
FIG. 22 is a timing diagram showing the operation of the logic circuit which is divided according to the prior art. Prior to the testing operation for Logic 1, Pausing Signal 1 is set at Low so that the initial value for the test as supplied from Scan-In Signal Line 1 can be input for Logic 1 (s2201). For pausing Logic 2 to Logic N, Pausing Signal 2 to Pausing Signal N are set at High (s2202). Thereafter during the testing operation for Logic 1, the result data for the test of Logic 1 is stored in the scan FF connected with Scan-In Signal Line 2. Next, the result data for the test of Logic 1 is collected by scan operation (s2203). This is followed by similar operation sequences for Logic 2 through Logic N.
Regardless, since there are overlaps of scan operations by scan FFs in the boundaries of the divided logic circuit, this method requires a longer test time. This counteracts the advantage of scanning because the time required for scan operation generally accounts for most of the overall test time.
As exemplified in FIG. 22, although a scan operation which uses Scan-In Signal Line 2 as an input can be accomplished during the test of Logic 1 (s2204), it must be done again during the test of Logic 2 (s2205). This results in an increase in the cost required for the test (the xe2x80x9ctest costxe2x80x9d).
As another potential solution, xe2x80x9cDesign for At-speed Test, Diagnosis and Measurementxe2x80x9d (Kluwer Academic Publishers, p.24, 1999) suggests a method of decreasing the frequency in scan operation to reduce power consumption. In this method, the frequency (s1903) of the system clock signal in the testing operation is not decreasedxe2x80x94only the frequency (s1901) of the system clock signal in the scan operation is decreased.
However, this method cannot reduce power consumption in the testing operation. As discussed above, the prior art has not properly addressed the problem of the extensive amount of time required for fault detection of a divided Logic circuit.
In at least one embodiment, the present invention preferably provides a semiconductor integrated circuit device in which the test cost can be reduced by reducing the required test time in relation to the prior art. The present invention also comprises fault-detecting methodologies thereof.
According to at least one preferred embodiment of the present invention, a semiconductor integrated circuit device comprises a storage element which constitutes a scan flip-flop, wherein the storage element has a selector for selectively picking up its output signals fed back thereto.
According to at least one embodiment of the present invention, a semiconductor integrated circuit device comprises storage elements and logic gates which constitute a scan flip-flop, wherein a first signal, the output signal of a first storage element, and a second signal are input into a first logic gate. The output signal of the first logic gate, and a third and a fourth signal are input into a second logic gate, and the output signal of the second logic gate and a fifth signal are input into the first storage element.
The above configuration may be characterized in that the output signal of the first storage element, the output signal of the second storage element, and the fourth signal are input into a third logic gate, and the output signal of the third Logic gate and the fifth signal are input into the second storage element. Additionally, the output signal of the first storage element and the fifth signal may be input into the second storage element.
According to at least one embodiment of the present invention, the above configuration is characterized in that the first logic gate consists of a first selector for selecting, through the first signal, whether to pick up the output signal of the first storage element or the second signal, and the second logic gate consists of a second selector for selecting, through the fourth signal, whether to pick up the output signal of the first logic gate or the third signal. Also, the embodiment may be characterized in that the third logic gate consists of a third selector for selecting, through the fourth signal, whether to pick up the output signal of the first storage element or the output signal of the second storage element.
According to another embodiment of the present invention, a semiconductor integrated circuit device comprises storage elements and logic gates which constitute a scan flip-flop, wherein: a first signal, a second signal, and a third signal are input into a first logic gate; a fourth signal and a fifth signal are input into a second logic gate; and the output signal of the first logic gate and the output signal of the second logic gate are input into the first storage element. Additionally, the output signal of the first storage element and the output signal of the second logic gate may be input into the second storage element.
According to another embodiment of the present invention, a semiconductor integrated circuit device comprises storage elements and logic gates which constitute a scan flip-flop, wherein: a first signal, a second signal, and a third signal are input into a first logic gate; a fourth signal and a fifth signal are input into a second logic gate; the output signal of the second logic gate is input into a third logic gate; and the output signal of the first logic gate and the output signal of the third logic gate are input into the first storage element. Additionally, either the fourth signal or the fifth signal, whichever makes more signal transitions than the other, is input into a gate terminal as another terminal of one of the transistors constituting the second logic gate which has a terminal connected with the output terminal of the second logic gate.
According to still another embodiment of the present invention, a semiconductor integrated circuit device comprises storage elements and logic gates which constitute a scan flip-flop, wherein: a first signal, a second signal, and a third signal are input into a first logic gate; the output signal of the first logic gate is input into a second logic gate; the output signal of the first logic gate, a fourth signal, and a fifth signal are input into a third logic gate; the output signal of the second logic gate, the fourth signal, and the fifth signal are input into a fourth logic gate; and the output signal of the third logic gate and the output signal of the fourth logic gate are input into the first storage element.
In at least one embodiment of a fault-defecting method of the present invention, the fault-detecting method of a semiconductor integrated circuit device having a logic circuit including storage elements is characterized in that the logic circuit is divided into a plurality of circuit blocks and a common scan operation is carried out on these circuit blocks. A testing operation is also carried out on every circuit block on a time-division basis.
According to another embodiment of the present invention, a fault-detecting method of a semiconductor integrated circuit device having a logic circuit including storage elements is characterized in that the logic circuit is divided into N circuit blocks using (N+1) scan paths composed of scan flip-flops, and common scan operation is carried out on these circuit blocks. A testing operation is continuously carried out on the circuit blocks.
According to still another embodiment of the present invention, a fault-detecting method of a semiconductor integrated circuit device is characterized in that the logic circuit in the semiconductor integrated circuit device is divided into N circuit blocks using (N+1) scan paths composed of scan flip-flops each having selectors for selectively picking up storage elements"" output signals which are fed back to the storage elements, and a common scan operation is carried out on these circuit blocks. A testing operation is preferably continuously carried out on the circuit blocks.